1. Field of the Invention
This invention relates to a MES field effect transistor (hereinafter referred to as "FET") possessing an LDD (lightly doped drain) structure and a method for the production thereof and more particularly to a MESFET of the LDD structure provided directly below a gate with a buried layer for control of leak current.
2. Description of the Related Art
The MESFETs made of such compound semiconductors as GaAs have been showing a growing trend toward the decrease in channel length for the sake of improving the electrical characteristics of their own and exalting the adaptability thereof for integration (i.e. number of components per chip) in LSIs. In consequence of this trend, they have come to manifest the so-called short channel effect. The LDD structure using a lower impurity concentration in part of the drain region for repressing this short channel effect has been proposed. Further, a BPLDD structure has been proposed anew for precluding the current particularly flowing directly below a gate from leaking into a substrate in the LDD structure ["0.35 .mu.m WNx/W gate BPLDD GaAs MESFET for ultraspeed digital IC," Matsunaga et al., Technical Report Of IEICE, ED92 128, VW92 131 ICD92 119 (1993 01), pp 35-40]. The BPLDD structure has a p type buried layer formed below an n type carrier conducting layer and, by dint of this buried layer, precludes the current flowing directly below a gate from leaking into a substrate.
FIG. 1A is a cross section illustrating the essential part of a conventional GaAs MESFET possessed of this BPLDD structure. In FIG. 1A, 1 stands for a semi-insulating GaAs substrate, 2 for an n type active layer forming a transistor region, 3 for a p type buried layer of relatively low impurity concentration, 4 for a gate electrode made of metal of high melting point, and 5 for a source and a drain electrodes. The n-type active layer 2 is composed of high impurity concentration regions 2a underlying the source and the drain electrodes, a low impurity concentration n type regions 2b for the LDD structure, and an n.sup.- region 2c directly below the gate. The p type buried layer 3 functions as a layer for suppressing the current flowing through the substrate.
The conventional BPLDD structure configurated as described above is enabled by the presence of the p type buried layer 3 to prevent to a certain extent the current flowing directly below the gate from escaping in the form of leak current 6 into the Substrate. The prevention so attained, however, is not fully satisfactory. In an improved version of MESFET illustrated in FIG. 1B, a buried p layer 7 is given an increased impurity concentration for the sake of further curbing the leakage of the current into the substrate.
FIG. 2 is a graph showing the relation between the gate length (the length in the direction of carrier movement) and the gate voltage threshold V.sub.th and the relation between the gate length and the parasitic capacity C.sub.gs of each of the GaAs MESFETs configurated as illustrated in FIGS. 1A and 1B. The curve B1 of the graph represents the V.sub.th characteristics of the GaAs MESFET of the configuration shown in FIG. 1A, the curve C1 thereof the V.sub.th characteristics of the improved device shown in FIG. 1B, the curve B2 thereof the C.sub.gs characteristics of the device shown in FIG. 1A, and the curve C2 thereof the C.sub.gs, characteristics of the device shown in FIG. 1B. It is clear from this graph that the improved version of FET shown in FIG. 1B retains a high threshold voltage V.sub.th in spite of a small gate length as compared with the FET shown in FIG. 1A and, owing to this merit, fulfills the expected object of repressing the leak current and improving the short channel effect.
When the two FETs of FIG. 1A and FIG. 1B are compared in terms of the parasitic capacity C.sub.gs, it is found that the improved FET shown in FIG. 1B exhibited a notably increased parasitic capacity for a fixed gate length as compared with the FET shown in FIG. 1A. This increase may well be regarded as a natural consequence of the fact that the buried p layer 7 in the FET of FIG. 1B is possessed of high impurity concentration.
In the FET of the conventional LDD structure described above, an effort to repress the leak current directly below the gate and improve the short channel effect by forming a buried layer of high impurity concentration possessing a conduction type opposite to that of an active layer brings about a converse effect of increasing the parasitic capacity and consequently degrading the high frequency characteristics of the FET. The degradation of the high frequency characteristics constitutes a serious problem because the GaAs MESFET is expected to find utility particularly in high frequency regions.